1. Field of the Invention
The present invention relates to input and output buffers in an integrated circuit. More particularly, the present invention relates an integrated circuit having a field programmable gate array (FPGA) portion and a mask programmable portion, wherein the mask programmable portion provides specialized input and output buffer functions to the integrated circuit.
2. The Prior Art
In an integrated circuit die, signals are transferred into and out of the die by input and output buffers, respectively, configured as part of the integrated circuit within the die. The input and output buffers generally perform relatively standard functions that are useful on all inputs and outputs, however, any or all the input and output buffers may also be configured to perform a variety of specialized functions including voltage gain, current gain, level translation, delay, signal isolation or hysteresis.
As is well known in the art, an FPGA is a collection of groups of gates partitioned into logic function modules which may be configured by user programmable interconnect elements to implement a large variety of digital logic functions. A programmable interconnect architecture, comprising a plurality of initially uncommitted interconnect conductors is superimposed over the array of logic function modules to enable custom connections to be made among the input and outputs of individual ones of logic function modules by user programmable elements to form digital circuits. The user programmable interconnect elements in both the logic function modules and the interconnect architecture may take several forms, such as one time programmable antifuse elements, transistors, RAM cells, etc. These forms of user programmable interconnect elements are well known to those of ordinary skill in the art.
Examples of several aspects of antifuse based FPGA architectures are disclosed in U.S. Pat. No. 4,758,745 to El Gamal, et al., U.S. Pat. No. 4,873,459 to El Gamal, et al., U.S. Pat. No. 5,073,729 to Greene, et al., U.S. Pat. No. 5,083,083 to El Ayat, et al., and U.S. Pat. No. 5,132,571 to McCollum, et al., U.S. Pat. No. 5,172,014 to El Ayat, U.S. Pat. No. 5,187,393 to El Ayat, et al., U.S. Pat. No. 5,191,241 to McCollum, et al., U.S. Pat. No. 5,317,698 to Chan, et al., U.S. Pat. No. 5,367,208 to El Ayat, et al., U.S. Pat. No. 5,451,887 to El Ayat, et al., U.S. Pat. No. 5,477,165 to El Ayat, et al., U.S. Pat. No. 5,509,128 to Chan, et al., U.S. Pat. No. 5,510,730 to El Gamal, et al., U.S. Pat. No. 5,537,056 to McCollum, U.S. Pat. No. 5,570,041 to El Ayat, et al., Ser. No. 08/522,945 to El Ayat, et al., and Ser. No. 08/575,519, El Gamal, et al., assigned to the same assignee as the present invention, and expressly incorporated herein by reference.
An example of a transistor-interconnect-element based FPGA architecture is disclosed in U.S. Pat. No. 4,870,302 to Freeman. Products embodying this type of architecture are marketed by Xilinx, Inc. of San Jose, Calif. In this architecture, transistors controlled by RAM cells are selectively turned on to make interconnections between logic function modules. Another such example is found in U.S. Pat. No. 5,187,393 El Gamal, et al. which uses EPROM or EEPROM transistors.
In a conventional FPGA, logic function modules typically on the periphery of the array are configured to provide the input and output buffers having any or all of the functions recited above. The input and output buffers are connectable to the inputs and the outputs of the logic function modules via the programmable interconnect structure to allow signals to flow into and out of the programmed logic modules comprising the digital circuits of the FPGA for processing by these digital circuits.
The logic function modules may be any one of a variety of circuits, including, for example, the logic modules disclosed in U.S. Pat. No. 4,758,745 to El Gamal, et al., U.S. Pat. No. 4,873,459 to El Gamal, et al., U.S. Pat. No. 4,910,417 to El Gamal, et al., U.S. Pat. No. 5,015,885 to El Gamal, et al., U.S. Pat. No. 5,451,887 to El Ayat, et al., and U.S. Pat. No. 5,477,165 to El Ayat, et al., U.S. Pat. No. 5,055,718 to Galbraith, et al., U.S. Pat. No. 5,198,705 to Galbraith, et al., U.S. Pat. No. 5,440,245, to Galbraith, et al., U.S. Pat. No. 5,448,185 to Kaptanoglu, U.S. Pat. No. 5,479,113 to El Gamal, et al., U.S. Pat. No. 5,570,041 to El Ayat, et al., Ser. No. 08/505,820 to Galbraith, et al., and Ser. No. 08/522,945 to El Ayat, et al., now U.S. Pat. No. 5,606,206, assigned to the same assignee as the present invention, and expressly incorporated herein by reference.
Though it may be highly desirable, and even feasible, to provide each of the input and output buffers of an FPGA with a multitude of functional capabilities, significant resources of the FPGA must be consumed to provide the input and output buffers with the desired multitude of functions. Some of these resources are required to select and program the interconnect elements of the interconnect architecture and the logic modules being used to provide the desired functions of each input and output buffer. Generally, as the functional capability of each input and output buffer increases, so does the amount of programming and selection circuitry needed to program the interconnect elements in the logic function modules. Other of these resources are used by the logic function modules themselves.
Further, when a variety of input or output functions is provided at each pin of the integrated circuit die, the logic function modules which are provided to implement functions which are not selected for a particular input or output pin add additional capacitance and resistive delay. To avoid the additional capacitance and resistive delay associated with the logic function modules of non-selected input and output buffer functions, design choices have been made in the prior art wherein only a selected number of input and output buffer functions are provided to the inputs and outputs of the integrated circuit die.
This solution, however, to the problems of additional capacitance and resistive delay simply raises a new set of problems. The selection of a limited number of input and output buffer functions places constraints on the place and route algorithms used to implement the desired digital circuitry from the logic modules. As is well known in the art, optimizing the use of the available logic function modules in an FPGA, is a very important goal of FPGA circuit designers. The development of placement and route routines which will optimize the use of the logic modules in the FPGA is an expensive and time consuming process. Placing constraints on the functions which may be provided by the input and output buffers may not only substantially affect the utilization of the logic function modules, but, in a worst case, may keep the placement and routing algorithms from implementing the desired digital logic.
Finally, there are some input and output buffer functions that are desired, but cannot feasibly be implemented by logic function modules in an FPGA. An example of such an input buffer function input, includes an input buffer having analog inputs. An example of such an output buffer includes an output buffer that can be connected to a voltage substantially above Vcc.
It is, therefore, an object of the present invention to optimize the functional capability of the input and output buffers of the integrated circuit die minimizing the amount of program and selection circuitry needed to implement the input and output buffer circuitry.
It is another object of the present invention to optimize the functional capability of the input and output buffers of the integrated circuit die while minimizing the capacitance and resistive delay associated with the input and output buffer circuits.
It is yet another object of the present invention to provide input and output buffers to an FPGA with greater functional capability than can be feasibly implemented by logic function modules in the FPGA.
It is a further object of the present invention to provide input buffers to an FPGA having analog inputs.
It is another object of the present invention to provide output buffers of an FPGA connectable to a voltage substantially greater than Vcc.
It is a further object of the present invention to provide output buffers for an FPGA which inject less noise into the FPGA.
It is another object of the present invention to provide output buffers for an FPGA which have low power consumption.
According to the present invention, a mask programmed portion of an integrated circuit provides some of the input and output buffer functions to an FPGA portion of the integrated circuit to provide additional functional capability to the I/O buffers, and improves the flexibility, signal isolation, speed and power management of the FPGA architecture. In CMOS technology, the mask programmed portion comprises N-channel and P-channel MOS transistors that can be connected together to implement almost any type of I/O buffer function conceivable in CMOS technology.
According to the present invention, an integrated circuit die is partitioned into an FPGA portion and a mask programmable portion. In the FPGA portion, logic modules are connected to an interconnect structure comprising interconnect conductors.
In one aspect of the invention standard FPGA input buffers including for example level translation and power down, and a standard FPGA output buffer including a large drive and tri-state capability are disposed in the FPGA portion of the integrated circuit. It should be appreciated, however, that the functions implemented in the standard input and output buffers will depend upon the input and output functions required by the FPGA and the input and output functions provided by the mask programmable portion of the integrated circuit.
In another aspect of the present invention, disposed in the mask programmable portion of the integrated circuit are an input and output buffers having any of a number of specialized input functions. In the integrated circuit, interconnect conductors span both the FPGA portion and the masked programmed portion to connect the FPGA portion to the input and output buffers disposed in the mask programmed portion. In the FPGA portion, the interconnect conductors form intersections with the interconnect architecture formed by the interconnect conductors in the FPGA portion of the integrated circuit. Disposed at a number of these intersections are user programmable interconnect elements, such as a one time programmable antifuse element, transistors, RAM cells, etc. The use of programmable interconnect elements are employed to selectively connect the interconnect conductors to the interconnect architecture of the FPGA portion.
According to another aspect of the present invention, in the mask programmable portion, the input and/or output buffers of the mask programmable portion may either be connected to shared Vcc and ground power busses and/or be segregated to certain Vcc and ground power bus portions that are isolated from one another. Further, dedicated Vcc and ground power pads for certain I/O locations may provide selected input and/or output buffers separate busses to I/O pins.
It should be appreciated that the I/O buffer function circuits to be described herein may be provided to a single I/O pin or several I/O pins in the masked programmed portion of the integrated circuit, and the choice of the I/O buffers circuits to be included in the mask programmed portion will depend upon the I/O needs of the end user of the circuit. Accordingly, in the present inventions a variety of integrated circuits, each having a different mask programmed portion and the same general FPGA portion, are contemplated.